A conventional testing of semiconductor integrated circuit devices (large-scale integrated circuits, referred to below as LSIs) is directed to the revealing of a stack at fault on a signal line. A stack at fault is such a fault in which the logical value of a signal is stuck at a certain value without dependency upon an input state of a circuit. It is a low-speed test technique in which mainly an open-circuit fault or a short-circuit fault of a signal line is modeled and in which degeneration of a signal line to “1” or “0” is presupposed. With the improvement of the integration technique, such as the shrinking of transistor size, the integration density as well as the operation clock frequency of up-to-date LSIs is increasing. Hence, delay faults, which cannot be detected with the low-speed test technique, are becoming non-negligible. The delay fault is such a fault in which the change in a signal is not propagated between flip-flops within prescribed time. It is produced due to delay in individual elements or in the interconnection between the elements.
A test for detecting delay faults is carried out by analyzing whether or not a signal output from an output flip-flop, out of two flip-flops arranged in a circuit, has been latched by an input flip-flop of the two flip-flops within a prescribed time. It is now supposed that a circuit including a NAND circuit 24 and an OR circuit 25, connected across flip-flops 21 and 22, as shown in FIG. 1, is tested. An input of the NAND circuit 24 is connected to an output of the flip-flop 21, while its other input holds the level “1” during the test. An input of the OR circuit 25 is connected to an output of the NAND circuit 24, while its other input holds the “0” level during the test. An output of the OR circuit 25 is supplied to the flip-flop 22 and thereby latched at a preset timing.
It is supposed that the flip-flops 21 and 22 capture input data at a preset interval and output the so captured data. The flip-flop 21 outputs “0” during the time period ti, while outputting “1” during the time period ti+1. The NAND circuit 24 outputs “0” after an interconnect delay between elements and an element delay of the NAND circuit 24 itself, as from the flip-flop 21 has output “1”. The OR circuit 25 outputs “0” after an interconnect delay between elements and an element delay of the OR circuit 24 itself, as from the NAND circuit 24 has output “0”. The flip-flop 22 receives “0” after an interconnect delay between elements as from the time the OR circuit 25 has output “0”. If these delays are increased, an output of the OR circuit 25 does not get to the flip-flop 22 within the time period ti+1 which is the time as from outputting from the flip-flop 21 until latching by the flip-flop 22. Hence, if the flip-flop 22 cannot latch “0” after the time period ti+1 as from the time of outputting of the signal “1” from the flip-flop 21, it is decided that a delay fault has occurred between the flip-flops 21 and 22.
In this case, if a signal to be detected by the flip-flop 22 is not different from one latch timing to another, it cannot be determined whether or not a signal output from the flip-flop 21 has reached the flip-flop 22. It is therefore necessary to generate test data so that a value latched by the flip-flop 22 will differ from the value latched at the previous latch timing. That is, such a signal which takes different values to be received by the flip-flop 22 at two neighboring time points, referred to below as a two-pattern signal, needs to be set in the flip-flop 21.
There is known a scan-path method as a technique for facilitating LSI testing. In the scan path method, respective flip-flops in a circuit are connected in a serial chain and operates as a shift register. In testing, optional values are set from outside to the flip-flops, by utilizing the shift function and the results of the operation for these values are sampled by the flip-flops and delivered serially to outside. By observing the result of the operations, the circuit may be tested as to whether or not it is operating as normally.
For testing an LSI using the scan path method, a plural number of scan flip-flops, as flip-flops for test, are provided in the LSI. The aforementioned shift register may be composed by interconnecting input/output terminals of the scan flip-flops in series with one another. The scan flip-flops include, in addition to the normal operating function thereof as ordinary flip-flops, the scan operating function, in which the scan flip-flops operate as flip-flops constituting a shift register, which receives, as a data input, a scan-in signal SIN that is a pattern signal for testing and a scan clock SC as a clock for testing.
As a scan flip-flop, used for testing a semiconductor integrated circuit device (LSI), the JP Patent Kokai Publication No. JP-P2002-189059A describes the configuration of a master-slave scan flip-flop, including a master latch unit and a slave latch unit for temporarily holding an input signal. Referring to FIG. 2, the scan flip-flop includes a master latch section 1, a slave latch section 2, a first clock control section 3, a first scan control section 4, a second scan control section 5, a second clock control section 6 and a third scan control section 7. The scan flip-flop also includes inverters INV1 to INV7, as an output buffer and a transfer gate control signal generating circuit.
To the master latch section 1, the slave latch section 2, the first clock control section 3, and to the second clock control section 6, there are connected an output terminal P01 of the inverter INV3 for inverting a clock signal C, and an output terminal P02 of the inverter INV4 for inverting an output clock of the inverter INV3. To the master latch section 1 and the first scan control section 4, there are connected an input terminal H04 of a first scan clock SC1 and an output terminal P03 of the inverter INV5 inverting the first scan clock signal SC1. To the second scan control section 5 and to the third scan control section 7, there are connected an output terminal H05 of a second scan clock signal SC2 and an output terminal CB1 of the inverter INV6 inverting the second scan clock signal SC2.
An output data signal Q is output from the slave latch section 2 via a buffer circuit (inverter INV1) to a node N01. The slave latch section 2 outputs a scan-out signal SOT via a buffer circuit (inverter INV2) to a node N02. The output data signal Q and the scan-out signal SOT have phases reversed to each other.
The master latch section 1 includes inverters INV11 and INV12 and transfer gates TG11 and TG12, and temporarily hold a data signal D or the scan-in signal SIN. The inverter INV12 inverts an output signal of the inverter INV11 and outputs the so inverted signal. The transfer gates TG11 and TG12 are connected in series between an output of the inverter INV12 and an input of the inverter INV11. There are connected an output terminal P01 of the inverter INV3 and an output terminal P02 of the inverter INV4 to the transfer gate TG11, which is on/off controlled in synchronization with the clock signal C. There are connected the terminal H04 and the output terminal P03 of the inverter INV5 to the transfer gate TG12, which is on/off controlled in synchronization with the first scan clock signal SC1.
The slave latch section 2 includes inverters INV21 and INV22 and a transfer gate TG21, and temporarily holds an output signal of the master latch section 1 in synchronization with a clock signal C for normal operation or with the second scan clock signal SC2. The inverter INV22 inverts an output signal of the inverter INV21. The transfer gate TG21 is connected betweens an output of the inverter INV22 and an input of the inverter INV21. There are connected the output terminal P01 of the inverter INV3 and the output terminal P02 of the inverter INV4 to the transfer gate TG21, which is on/off controlled in synchronization with the clock signal C. An output signal of the inverter INV21 becomes the output data signal Q via the inverter INV1. An output signal of the inverter INV22 becomes the scan-out signal SOT through the inverter INV2. Also, an output signal of the inverter INV2 is fed back to the second clock control section 6 through a third scan control section 7.
The first clock control section 3 includes an inverter INV31 and a transfer gate TG31. The inverter INV31 inverts the data signal D. There are connected the output terminal P01 of the inverter INV3 and the output terminal P02 of the inverter INV4 to the transfer gate TG31, which is on/off controlled in synchronization with the clock signal C. The first clock control section 3 outputs the input data signal D to the master latch section 1 responsive to the clock signal C.
The first scan control section 4, receiving the scan-in signal SIN, includes a transfer gate TG41. There are connected the terminal H04 and the output terminal P03 of the inverter INV5 to the transfer gate TG41, which is on/off controlled in synchronization with the first scan clock signal SC1. The first scan control section 4 outputs the received scan clock signal SC1 to the master latch section 1, responsive to the first scan clock signal SC1.
The second scan control section 5, receiving an output signal of the master latch section 1, includes a transfer gate TG51. There are connected the terminal H05 and the output terminal CB1 of the inverter INV6 to the transfer gate TG51, which is on/off controlled in synchronization with the second scan clock signal SC2. The second clock control section 5 outputs an output signal of the master latch section 1 to the second clock control section 6, responsive to the second scan clock signal SC2.
The second clock control section 6, receiving an output signal of the second scan control section 5, includes a transfer gate TG61. There are connected the output terminal P01 of the inverter INV3 and the output terminal P02 of the inverter INV4 to the transfer gate TG61, which is on/off controlled in synchronization with the clock signal C. The second clock control section 6 outputs the output signal of the second scan control section 5 to the slave latch section 2, responsive to the clock signal C.
The third scan control section 7, receiving an output signal of the inverter INV22 of the slave latch section 2, includes a transfer gate TG71. There are connected the output terminal H05 and the output terminal CB1 of the inverter INV6 to the transfer gate TG71, which is on/off controlled in synchronization with the second scan clock signal SC2. The third scan control section 7 outputs the received output signal of the inverter INV22 to the second clock control section 6, responsive to the second scan clock signal SC2.
The master latch section 1, first clock control section 3 and the first scan control section 4 constitute a circuit for temporarily holding the input data signal D, responsive the clock signal C, while constituting a circuit for temporarily holding the scan-in signal SIN, responsive to the scan clock signal SC1. The slave latch section 2, second scan control section 5, second clock control section 6 and the third scan control section 7 constitute a circuit for temporarily holding the output signal of the master latch section 1, responsive to the clock signal C, while constituting a circuit for temporarily holding an output signal of the master latch section 1, responsive to the second scan clock signal SC2.
Each transfer gate is composed by a P-channel MOS transistor and an N-channel MOS transistor, in which a source and a drain of the P-channel MOS transistor are connected to a drain and a source of the N-channel MOS transistor. The transfer gate acts as a switch on/off controlled responsive to a control signal applied to the gates of the P-channel MOS transistor and the N-channel MOS transistor.
The operation of the conventional scan flip-flop will now be described. During the normal operation of the scan flip-flop, the first scan clock signal SC1 and the second scan clock signal SC2 are maintained at LOW level and at HIGH level, respectively. Thus, the transfer gate TG12 of the master latch section 1 and the transfer gate TG51 of the second scan control section 5 are maintained in an on-state, while the transfer gate TG41 of the first scan control section 4 and the transfer gate TG71 of the third scan control section 7 are maintained in an off-state.
In these states, the input data signal D (HIGH level or LOW level) is received from a terminal H01. When the clock signal C falls to LOW level, the transfer gate TG31 of the first clock control section 3 is rendered conductive, that is, turned on, while the transfer gate TG11 is rendered non-conductive, that is, turned off. Hence the input data signal D is supplied as input to the master latch section 1, through the transfer gate TG31. The master latch section 1 causes a signal, received from the first clock control section 3, to be inverted by inverter INV1, and outputs the so inverted signal to the second scan control section 5.
Since the second scan clock signal SC2 is at HIGH level, the transfer gate TG51 of the second scan control section 5 is maintained in an on-state, so that an output signal of the master latch section 1 is supplied as input to the second clock control section 6. Since the clock signal C is at LOW level, the transfer gate TG61 of the second clock control section 6 is in an off-state, and hence the transfer gate TG21 of the slave latch section 2 is in an on-state. Consequently, the slave latch section 2 keeps its internal state, such that its output signals Q and SOT remain unchanged.
When next the clock signal C rises to HIGH level, the transfer gate TG31 of the first clock control section 3 is rendered non-conductive, that is, turned off, while the transfer gate TG11 is rendered conductive, that is, turned on. Hence, the input data signal D ceases to be supplied to the master latch section 1, however, the output signal of the inverter INV12 is supplied via the transfer gates TG12 and TG11 to the input of the inverter INV11. That is, since the output signal of the inverter INV12 is fed back to the input of the inverter INV11, the master latch section 1 maintains a value (HIGH level or LOW level), directly previous to the rise of the clock signal C, as its internal state.
At this time, the transfer gate TG61 of the second clock control section 6 is rendered conductive, that is, turned on. The transfer gate TG21 of the slave latch section 2 is rendered non-conductive, that is, turned off, so that the slave latch section 2 captures an output of the master latch section 1, supplied from the second scan control section 5. The slave latch section 2 inverts a signal, received via the second clock control section 6, by the inverter INV21, and outputs the so inverted signal. This output signal is further inverted by the inverter INV1 so as to be output at terminal N01 as output data signal Q. This output signal is also inverted by the inverter INV22 so as to be output to the third scan control section 7and to the inverter INV2. An output signal of the inverter INV2 is output from a node N02 as inverted output data signal QB or scan output signal SOT.
When the clock signal C rises to HIGH level again, the transfer gate TG61 of the second clock control section 6 is rendered non-conductive, that is, turned off, while the transfer gate TG21 of the slave latch section 2 is rendered conductive, that is, turned on. An output signal of the inverter INV21 is fed back via the inverter INV22 and transfer gate TG21 to an input of the inverter INV21. Hence, the slave latch section 2 holds its internal state it has taken in, with its output signals Q and SOT remaining unchanged.
The operation of the scan flip-flop at the time of the scan operation will now be described with reference to FIG. 3. During the scan operation, the clock signal C is maintained at HIGH level. Thus, the transfer gate TG11 of the master latch section 1 and the transfer gate TG61 of the second clock control section 6 are kept in a conductive state, that is, in an on-state, while the transfer gate TG31 of the first clock control section 3 and the transfer gate TG21 of the slave latch section 2 are kept in a non-conductive state, that is, in an off-state. Under these conditions, the scan-in signal SIN is supplied from the terminal H03. The scan-in signal SIN goes HIGH during a time period p1.
When the first scan clock signal SC1 rises to HIGH level (time period p2), the transfer gate TG41 of the first scan control section 4 is rendered conductive, that is, turned on, while the transfer gate TG12 of the master latch section 1 is rendered non-conductive, that is, turned off. Thus, the scan-in signal SIN is supplied through transfer gate TG11 to the inverter INV11. An output node Na of the inverter INV11 goes LOW. Since the second scan clock signal SC2 at this time is at LOW level, the transfer gate TG11 of the second scan control section 5 is in a non-conductive state, that is, in an off-state, so that the slave latch section 2 remains unchanged.
When the first scan clock signal SC1 rises to LOW level (time period t3), the transfer gate TG41 is in a non-conductive state, that is, turned off, while the transfer gate TG12 is in a conductive state, that is, turned on. An output signal of the inverter INV12 is fed back to an input of the inverter INV1, through transfer gates TG11 and TG12, and is kept at a value which prevailed when the first scan clock signal SC1 was at HIGH level, that is, just before the first scan clock signal SC1 transitioned to LOW level. That is, the master latch section 1 holds the state of the scan-in signal SIN it has taken in during the time period p2. The master latch section 1 keeps on holding this internal state as long as the first scan clock signal SC1 is at LOW level (time periods t3 through t5).
The second scan clock signal SC2 then rises to HIGH level (time period p4). The transfer gate TG51 of the second scan control section 5 then is conductive, that is, turned on, while the transfer gate TG71 of the third scan control section 7 then is non-conductive, that is, turned off. Hence, the second scan control section 5 supplies an output of the master latch section 1 through the transfer gate TG61 of the second clock control section 6 to the slave latch section 2.
The slave latch section 2 inverts the signal, received from the inverter INV21, to output the resulting signal to the inverter INV1, while supplying the signal to the inverter INV22. The inverter INV1 further inverts the signal to output the output data signal Q as an LOW level signal. The signal supplied to the inverter INV22 is inverted and supplied to the third scan control section 7 and to the inverter INV2. The inverter INV2 outputs the scan-out signal SOT, as a HIGH level signal, which is reverse phased with respect to the output data signal Q.
When the second scan clock signal SC2 falls to LOW level (timer period p5), the transfer gate TG51 is rendered non-conductive, that is, turned off, while the transfer gate TG51 is rendered conductive, that is, turned on. Hence, the signal supplied from the master latch section 1 is cut off, and the output signal of the inverter INV22 is supplied via the transfer gate TG71 to the second clock control section 6. The transfer gate TG61 supplies an output signal of the inverter INV22 to the inverter INV21. Hence, the output signal of the inverter INV21 is inverted by the inverter INV22 and fed back to the input of the inverter INV21 through transfer gates TG71 and TG61. Hence, the slave latch section 2 is kept at a value which prevailed when the second scan clock signal SC2 was at HIGH level, that is, just before the second scan clock signal SC2 was turned to LOW level. That is, the slave latch section 2 holds the state of the output signal of the master latch section 1 that was captured during the time period p4. This signal holding state is continued as long as the second scan clock signal SC2 is at LOW level (time periods p5 through p7).
Thus, with the conventional scan flip-flop, the scan-in signal SIN is sampled when the first scan clock signal SC1 is at HIGH level. The so sampled scan-in signal is temporarily retained in the master latch section 1. Also, in the conventional scan flip-flop, the slave latch section 2 takes over the internal state of the master latch section 1 when the second scan clock signal SC2 is at HIGH level, and the slave latch section 2 then outputs the internal state as the scan-out signal SOT. The conventional scan flip-flop repeats this sequence of operations to carry out the shift operations.
Referring to FIG. 4, a delay fault test, carried out in a scan path, made up of three stages of conventional scan flip-flops 14, 15 and 16, operated as described above, will now be described. The scan flip-flops 14, 15 and 16 are operated as a shift register, during the scan-pass test, as the scan-in terminals SIN and the scan-out terminals SOT thereof are connected with one another as shown. A combinational circuit 18 is connected between the scan flip-flops 14 and 15, whilst another combinational circuit 19 is connected between the scan flip-flops 15 and 16. The combinational circuit 18 carries out combinational logic operations on an output signal Q14 of the scan flip-flop 14, to output a signal D18 representing the result of the operations. The combinational circuit 19 carries out combinational logic operations on an output signal Q15 of the scan flip-flop 15, to output a signal D19 representing the result of the operations. The clock signal C, first scan clock signal SC1 and the second scan clock signal SC2 are supplied in common to the scan flip-flops 14 to 16. When the scan flip-flops 14 to 16 are operated as shift register, a scan-in signal SI and a scan-out signal are serially input and output, respectively.
FIG. 5 is a timing chart showing the operation of a conventional delay fault test. For the scan flip-flops, test data of patterns “A”, “B” and “C” are set. For setting the test data for the respective scan flip-flops, the first scan clock signal SC1 and the second scan clock signal SC2 are supplied. That is, HIGH level pulses SC1a, SC2a, SC1b, SC2b, SC1c and SC2c are applied as shift clocks for the respective scan flip-flops ((b) and (c) of FIG. 5). The clock signal C is kept at this time at HIGH level ((a) of FIG. 5). The test data “A”, “B” and “C” are shifted in order from the scan flip-flop 14 to the scan flip-flop 15 and from the scan flip-flop 15 to the scan flip-flop 16, in synchronization with the rising of the pulses SC2a, SC2b and SC2c, respectively ((e), (g) and (i) of FIG. 5). It is noted that data received at the scan-in terminal SIN (node H03) are output at the output data terminal Q (node N01) with inverted polarity and hence are designated with suffixes n.
At a rise time point of the pulse SC2c, test data “C”, “B” and “A” are set in the scan flip-flops 14, 15 and 16, respectively. The clock signal C is once set to LOW level, at a preset timing Ca, in order to operate the circuit with first pattern data ((a) of FIG. 5). Each scan flip-flop captures data from the input data signal terminal D (node H01) when the clock signal C is at LOW level. When the clock rises to HIGH level, the scan flip-flop outputs the data as output data signal Q. Thus, the output data signal Q14, output from the scan flip-flop 14, is changed to “Dn” which has been applied to the input data terminal D of the scan flip-flop 14 ((e) of FIG. 5). An output data signal Q16, output from the scan flip-flop 15, is changed to “C1n”, by taking in a result signal D18 representing the result of operation by the combinational circuit 18 on the output data signal Q14=“Cn” of the scan flip-flop 14 ((g) of FIG. 5). The scan-out signal SO, output from the scan flip-flop 16, is changed to “B2” by taking in a result signal D19 representing the result of operation by the combinational circuit 19 on the output data signal Q15=“Bn” of the scan flip-flop 15 ((i) of FIG. 5).
At a timing Cb after lapse of a preset time T as from timing Ca, the clock signal C again becomes LOW level. The output data signal Q14, output from the scan flip-flop 14, is changed to “EN” so far applied to the input data terminal D of the scan flip-flop 14 ((e) of FIG. 5). An output data signal Q16, output from the scan flip-flop 15, is changed to “D1n”, by taking in a result signal D18 representing the result of operation by the combinational circuit 18 on the output data signal Q14=“Dn” of the scan flip-flop 14 ((g) of FIG. 5). The scan-out signal SO, output from the scan flip-flop 16, is changed to “C2”, by taking in a result signal D19 representing the result of operation by the combinational circuit 19 on the output data signal Q15=“C1n” of the scan flip-flop 15 ((i) of FIG. 5).
When the clock signal C reverts to HIGH level, the second scan clock signal SC2 becomes LOW level. The master latch units 1 and the slave latch units 2 of the respective scan flip-flop retain their respective states ((c) of FIG. 5). The first scan clock signal SC1 and the second scan clock signal SC2 then apply pulses SC1d, SC2d, SC1e and SC2e to the respective scan flip-flops in order to serially output the test results set in the respective scan flip-flops. The output data signal Q15 of the scan flip-flop 15 is changed to “D1n” and then into “En”, in synchronization with the rising of the pulses SC2d and SC2e, while the scan-out signal SO of the scan flip-flop 15 is changed to “C2”, then to “D1” and then to “E”. That is, the values at capturing time points when the second clock signal C has become LOW are serially output in order as the scan-out signal SO.
The sampled value at the rise time points of the second clock signal C represent a test result of the delay fault test. That is, input data for a circuit being tested need to be supplied so that the output of the circuit being tested for delay fault will be changed. Since the circuit being tested is the combinational circuit 19, the data “C2n” output on inputting “C1n” must be different from the data “D2n” output on inputting “D1n”. The data “D1n” is the result of operation by the combinational circuit 18 on the output signal Q14 of the scan flip-flop 14. Hence, in testing the combinational circuit 19, it is necessary to perform reverse-operation with respect to the operation executed by the combinational circuit 18 to find test data to be supplied to the scan flip-flop 14.
[Patent Document 1] JP Patent Kokai Publication No. JP-P2002-189059A